1. Field of the Invention
The present invention relates to a semiconductor device provided with a DRAM cell having a trench capacitor and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell provided with a trench capacitor comprises a semiconductor substrate formed with a deep trench and a capacitor formed in a deep inside of the trench. Regarding the capacitor, a capacitor insulating film is formed on a deep inside surface of the trench. A first electrode layer is buried inside the capacitor insulating film, whereby the capacitor is fabricated. Furthermore, a second electrode layer is formed on the first electrode layer. A collar insulating film is formed in order to retain an insulation performance between the semiconductor substrate and the first and second electrode layers buried inside the trench.
JP-A-2003-60079 discloses a capacitor manufacturing method. In the disclosed method, a capacitor insulating film, collar insulating film and electrode layer are formed in a trench as follows. Firstly, a deep trench (corresponding to a trench) is formed in a substrate (corresponding to a semiconductor substrate). Subsequent to several steps, a capacitor dielectric layer (corresponding to a capacitor insulating film) is formed on an inner surface of the deep trench. A conductive layer (corresponding to an electrode layer) is formed so as to fill the deep trench. At this time, a gap occurs in the conductive layer. Subsequently, a part of the conductive layer corresponding to an upper portion of the deep trench is removed while a part of the conductive layer corresponding to a bottom of the deep trench.
Furthermore, a colored oxidation layer (corresponding to a collar insulating film) is formed and a colored liner layer made of a material differing from the colored oxidation layer is also formed. A part corresponding to the upper conductive layer is removed. In this case, an oxide is present in the gap. Accordingly, when the conductive layer is formed on the gap, there is a possibility that electric connection cannot be obtained. In view of the possibility, the colored oxidation layer of a part corresponding to the gap is removed.
In the manufacturing method of JP-A-2003-60079, the capacitor dielectric layer is formed as the capacitor insulating film, and the colored oxidation layer and colored liner layer are formed as the collar insulating film. Generally, in the DRAM cell with a trench capacitor, a collar insulating film is formed so as to be thinner than a capacitor insulating film so that an insulating performance is retained between a storage electrode and the semiconductor substrate. The capacitor insulating film needs to be formed to be thinner than the collar insulating film in order that a capacity of the trench capacitor may be increased. As a result, the method disclosed in JP-A-2003-60079 needs to be applied. However, the above-noted manufacturing method results in much trouble and cost increase.